1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method of fabricating a silicide layer on a substrate.
2. Description of the Related Art
A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The substrate is annealed to activate the dopant in the source and the drain. Dielectric sidewall spacers are frequently formed adjacent to the gate electrode to serve as implant masks and barriers to hot carriers.
The interfaces between structures of a transistor implemented in silicon or polysilicon, such as source/drain regions and poly gates, and local or global interconnects typically exhibit relatively high series sheet resistances. The resistances can lead to undesirably high power consumption and heat propagation in integrated circuits. One method in use for years to reduce the series resistance of these types of structural interfaces involves the fabrication of metal-silicide layers on sources and drains, and on gate electrodes where polysilicon is the material of choice. Self-aligned silicidation ("salicidation") is perhaps the most common application of this method.
In conventional salicidation, a metal capable of reacting with silicon, such as titanium, is deposited on the gate, the sidewall spacers, and the source and drain regions. A one or two step anneal is performed to react the titanium with the polysilicon of the gate and the silicon of the source and drain regions to form TiSi.sub.2. Following the anneal, an etch is performed to remove any unreacted titanium.
In addition to serving as implant masks, one of the principal functions of sidewall spacers is to separate the silicided gate from the source/drain regions. Despite the incorporation of spacers, silicide may form laterally and easily bridge the separation between the polysilicon gate electrode and the silicon source/drain regions causing the gate to become shorted to the source/drain regions. This so-called "bridging effect" occurs where silicon diffuses into the titanium regions that cover the sidewall spacers and subsequently reacts with the titanium.
Certain conditions tend to favor lateral TiSi.sub.2, formation. Conventional furnace annealing in an inert gas atmosphere (e.g., argon for approximately 30 minutes) may foster rapid lateral TiSi.sub.2 formation. Processing in the sub-0.25 .mu.m domain also appears to raise the frequency of lateral silicide formation. In sub-0.25 .mu.m processing, the minimum gate width may approach or even reach the dimensions of the grain boundaries between the individual grains of the polycrystalline silicon gate electrode. As the minimum device size approaches the dimensions of the grain boundaries in the polysilicon, the rate of silicon diffusion from the polysilicon into the titanium increases. The increased diffusivity is believed to stem from the elimination of pluralities of intersecting polysilicon grain boundaries that are present in larger scale processes. These grain boundaries act as natural barriers to silicon diffusion.
Cobalt silicide processing has gained some recognition as a potential replacement for TiSi.sub.2 in salicidation processing. Cobalt silicide provides acceptable values of sheet resistance and presents much lower risk of bridging. However, conventional CoSi.sub.2 processing is not without disadvantages. Most conventional methods are similar to conventional TiSi.sub.2 processing in that a layer of cobalt is deposited on silicon and/or polysilicon and annealed to trigger conversion to cobalt silicide. During the anneal, cobalt and/or cobalt silicide can quickly diffuse down into the substrate and form conducting filaments that penetrate the pn junctions of a source drain region. Depending on their depth, size and number, such filaments can cause unacceptably high reverse-bias diode-leakage currents.
The conventional technique for compensating for cobalt silicide filament formation is to ensure that the pn junctions of source/drain regions are positioned below the deepest anticipated filament penetration. The determination of the maximum anticipated filament depth involves some guess work. Moreover, placing depth constraints on pn junction depth represents a real impediment to transistor geometry scaling.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.